/**
 ******************************************************************************
 * @file    zb32l03x_hal_qspi.h
 * @author  Application Team
 * @Version V1.0.0
 * @Date    2022/08/31
 * @brief   Header file of QSPI HAL module.
 ******************************************************************************
 **/

#ifndef __ZB32L03x_HAL_QSPI_H
#define __ZB32L03x_HAL_QSPI_H

#ifdef __cplusplus
extern "C" {
#endif

#include "zb32l03x_hal_def.h"


/** @defgroup QSPI_Exported_Types QSPI Exported Types
 * @{
 */



/**
 * @brief HAL QSPI State structure definition
 */
typedef enum
{
    HAL_QSPI_STATE_RESET                = 0x00U,    /*!< Peripheral not initialized                            */
    HAL_QSPI_STATE_READY                = 0x10U,    /*!< Peripheral initialized and ready for use              */
    HAL_QSPI_STATE_BUSY                 = 0x20U,    /*!< Peripheral in indirect mode and busy                  */
    HAL_QSPI_STATE_BUSY_INDIRECT_TX     = 0x21U,    /*!< Peripheral in indirect mode with transmission ongoing */
    HAL_QSPI_STATE_BUSY_INDIRECT_RX     = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */
    HAL_QSPI_STATE_BUSY_AUTO_POLLING    = 0x24U,    /*!< Peripheral in auto polling mode ongoing               */
    HAL_QSPI_STATE_BUSY_MEM_MAPPED      = 0x28U,    /*!< Peripheral in memory mapped mode ongoing              */
    HAL_QSPI_STATE_ABORT                = 0x40U,    /*!< Peripheral with abort request ongoing                 */
    HAL_QSPI_STATE_TIMEOUT              = 0x80U,    /*!< Timeout state                                         */
    HAL_QSPI_STATE_ERROR                = 0x100U    /*!< error                                                 */
} HAL_QSPI_StateTypeDef;


/**
 * @brief  HAL QSPI Sample Shifting structure definition
 */
typedef enum
{
    HAL_QSPI_SAMPLE_SHIFTING_NONE       = 0x00000000U,          /*!< No clock cycle shift to sample data*/
    HAL_QSPI_SAMPLE_SHIFTING_HALFCYCLE  = QUADSPI_CR_SSHIFT     /*!< 1/2 clock cycle shift to sample data*/
} HAL_QSPI_SampleShiftingTypeDef;


/**
 * @brief  HAL QSPI ChipSelect High Time structure definition
 */
typedef enum
{
    HAL_QSPI_CS_HIGH_TIME_1_CYCLE   = 0x00000000U,                          /*!< nCS stay high for at least 1 clock cycle between commands*/
    HAL_QSPI_CS_HIGH_TIME_2_CYCLE   = (0x1UL << QUADSPI_DCR_CSHT_Pos),      /*!< nCS stay high for at least 2 clock cycles between commands*/
    HAL_QSPI_CS_HIGH_TIME_3_CYCLE   = (0x2UL << QUADSPI_DCR_CSHT_Pos),      /*!< nCS stay high for at least 3 clock cycles between commands*/
    HAL_QSPI_CS_HIGH_TIME_4_CYCLE   = (0x3UL << QUADSPI_DCR_CSHT_Pos),      /*!< nCS stay high for at least 4 clock cycles between commands*/
    HAL_QSPI_CS_HIGH_TIME_5_CYCLE   = (0x4UL << QUADSPI_DCR_CSHT_Pos),      /*!< nCS stay high for at least 5 clock cycles between commands*/
    HAL_QSPI_CS_HIGH_TIME_6_CYCLE   = (0x5UL << QUADSPI_DCR_CSHT_Pos),      /*!< nCS stay high for at least 6 clock cycles between commands*/
    HAL_QSPI_CS_HIGH_TIME_7_CYCLE   = (0x6UL << QUADSPI_DCR_CSHT_Pos),      /*!< nCS stay high for at least 7 clock cycles between commands*/
    HAL_QSPI_CS_HIGH_TIME_8_CYCLE   = (0x7UL << QUADSPI_DCR_CSHT_Pos),      /*!< nCS stay high for at least 8 clock cycles between commands*/
} HAL_QSPI_CS_HighTimeTypeDef;


/**
 * @brief  HAL QSPI Clock Mode structure definition
 */
typedef enum
{
    HAL_QSPI_CLOCK_MODE_0   = 0x00000000U,          /*!< Clk stays low while nCS is released*/
    HAL_QSPI_CLOCK_MODE_3   = QUADSPI_DCR_CKMODE    /*!< Clk goes high while nCS is released*/
} HAL_QSPI_ClockModeTypeDef;


/**
 * @brief  HAL QSPI Flash Select structure definition
 */
typedef enum
{
    HAL_QSPI_FLASH_BK_1     = 0x00000000U,      /*!< FLASH BK 1 selected*/
    HAL_QSPI_FLASH_BK_2     = QUADSPI_CR_FSEL   /*!< FLASH BK 2 selected*/
} HAL_QSPI_FlashBKTypeDef;


/**
 * @brief  HAL QSPI Dual Flash Mode structure definition
 */
typedef enum
{
    HAL_QSPI_DUALFLASH_ENABLE   = QUADSPI_CR_DFM,   /*!< Dual-flash mode enabled*/
    HAL_QSPI_DUALFLASH_DISABLE  = 0x00000000U       /*!< Dual-flash mode disabled*/
} HAL_QSPI_DualFlashTypeDef;


/**
 * @brief  HAL QSPI Address Size structure definition
 */
typedef enum
{
    HAL_QSPI_ADDRESS_8_BITS     = 0x00000000U,                          /*!< 8-bit address*/
    HAL_QSPI_ADDRESS_16_BITS    = (0x1UL << QUADSPI_CCR_ADSIZE_Pos),    /*!< 16-bit address*/
    HAL_QSPI_ADDRESS_24_BITS    = (0x2UL << QUADSPI_CCR_ADSIZE_Pos),    /*!< 24-bit address*/
    HAL_QSPI_ADDRESS_32_BITS    = (0x3UL << QUADSPI_CCR_ADSIZE_Pos)     /*!< 32-bit address*/
} HAL_QSPI_AddressSizeTypeDef;


/**
 * @brief  HAL QSPI Alternate Bytes Size structure definition
 */
typedef enum
{
    HAL_QSPI_ALTERNATE_BYTES_8_BITS     = 0x00000000U,                          /*!< 8-bit alternate bytes*/
    HAL_QSPI_ALTERNATE_BYTES_16_BITS    = (0x1UL << QUADSPI_CCR_ABSIZE_Pos),    /*!< 16-bit alternate bytes*/
    HAL_QSPI_ALTERNATE_BYTES_24_BITS    = (0x2UL << QUADSPI_CCR_ABSIZE_Pos),    /*!< 24-bit alternate bytes*/
    HAL_QSPI_ALTERNATE_BYTES_32_BITS    = (0x3UL << QUADSPI_CCR_ABSIZE_Pos)     /*!< 32-bit alternate bytes*/
} HAL_QSPI_AlternateByteSizeTypeDef;


/**
 * @brief  HAL QSPI Instruction Mode structure definition
 */
typedef enum
{
    HAL_QSPI_INSTRUCTION_NONE       = 0x00000000U,                          /*!< No instruction*/
    HAL_QSPI_INSTRUCTION_1_LINE     = (0x1UL << QUADSPI_CCR_IMODE_Pos),     /*!< Instruction on a single line*/
    HAL_QSPI_INSTRUCTION_2_LINES    = (0x2UL << QUADSPI_CCR_IMODE_Pos),     /*!< Instruction on two lines*/
    HAL_QSPI_INSTRUCTION_4_LINES    = (0x3UL << QUADSPI_CCR_IMODE_Pos)      /*!< Instruction on four lines*/
} HAL_QSPI_InstructionModeTypeDef;


/**
 * @brief  HAL QSPI Address Mode structure definition
 */
typedef enum
{
    HAL_QSPI_ADDRESS_NONE           = 0x00000000U,                          /*!< No address*/
    HAL_QSPI_ADDRESS_1_LINE         = (0x1UL << QUADSPI_CCR_ADMODE_Pos),    /*!< Address on a single line*/
    HAL_QSPI_ADDRESS_2_LINES        = (0x2UL << QUADSPI_CCR_ADMODE_Pos),    /*!< Address on two lines*/
    HAL_QSPI_ADDRESS_4_LINES        = (0x3UL << QUADSPI_CCR_ADMODE_Pos)     /*!< Address on four lines*/
} HAL_QSPI_AddressModeTypeDef;


/**
 * @brief  HAL QSPI Alternate Bytes Mode structure definition
 */
typedef enum
{
    HAL_QSPI_ALTERNATE_BYTES_NONE       = 0x00000000U,                          /*!< No alternate bytes*/
    HAL_QSPI_ALTERNATE_BYTES_1_LINE     = (0x1UL << QUADSPI_CCR_ABMODE_Pos),    /*!< Alternate bytes on a single line*/
    HAL_QSPI_ALTERNATE_BYTES_2_LINES    = (0x2UL << QUADSPI_CCR_ABMODE_Pos),    /*!< Alternate bytes on two lines*/
    HAL_QSPI_ALTERNATE_BYTES_4_LINES    = (0x3UL << QUADSPI_CCR_ABMODE_Pos)     /*!< Alternate bytes on four lines*/
} HAL_QSPI_AlternateByteModeTypeDef;


/**
 * @brief  HAL QSPI Data Mode structure definition
 */
typedef enum
{
    HAL_QSPI_DATA_NONE              = 0x00000000U,                          /*!< No data*/
    HAL_QSPI_DATA_1_LINE            = (0x1UL << QUADSPI_CCR_DMODE_Pos),     /*!< Data on a single line*/
    HAL_QSPI_DATA_2_LINES           = (0x2UL << QUADSPI_CCR_DMODE_Pos),     /*!< Data on two lines*/
    HAL_QSPI_DATA_4_LINES           = (0x3UL << QUADSPI_CCR_DMODE_Pos)      /*!< Data on four lines*/
} HAL_QSPI_DataModeTypeDef;


/**
 * @brief  HAL QSPI SIOO Mode structure definition
 */
typedef enum
{
    HAL_QSPI_SIOO_INST_EVERY_CMD        = 0x00000000U,          /*!< Send instruction on every transaction*/
    HAL_QSPI_SIOO_INST_ONLY_FIRST_CMD   = QUADSPI_CCR_SIOO      /*!< Send instruction only for the first command*/
} HAL_QSPI_SIOOModeTypeDef;


/**
 * @brief  HAL QSPI Match Mode structure definition
 */
typedef enum
{
    HAL_QSPI_MATCH_MODE_AND         = 0x00000000U,      /*!< AND match mode between unmasked bits*/
    HAL_QSPI_MATCH_MODE_OR          = QUADSPI_CR_PMM    /*!< OR match mode between unmasked bits*/
} HAL_QSPI_MatchModeTypeDef;


/**
 * @brief  HAL QSPI Automatic Stop structure definition
 */
typedef enum
{
    HAL_QSPI_AUTOMATIC_STOP_DISABLE  = 0x00000000U,     /*!< AutoPolling stops only with abort or QSPI disabling*/
    HAL_QSPI_AUTOMATIC_STOP_ENABLE   = QUADSPI_CR_APMS  /*!< AutoPolling stops as soon as there is a match*/
} HAL_QSPI_AutoPollingStopTypeDef;


/**
 * @brief  HAL QSPI Timeout Activation structure definition
 */
typedef enum
{
    HAL_QSPI_TIMEOUT_COUNTER_DISABLE    = 0x00000000U,      /*!<Timeout counter disabled, nCS remains active*/
    HAL_QSPI_TIMEOUT_COUNTER_ENABLE     = QUADSPI_CR_TCEN   /*!<Timeout counter enabled, nCS released when timeout expires*/
} HAL_QSPI_TimeoutActivationTypeDef;


/**
 * @brief  QSPI Init Configuration structure definition
 */
typedef struct
{
    uint32_t                        ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
                                                            This parameter can be a number between 0 and 255 */
    uint32_t                        FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode).
                                                            When indirect READ mode, H/w set FIF flag if FIFO_Count > threshold.
                                                            When indirect WRITE mode, H/w set FIF flag if (32 - FIFO_Count) < threshold.
                                                            This parameter can be a value between 1 and 16 */
    HAL_QSPI_SampleShiftingTypeDef  SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
                                                            take in account external signal delays. (It should be HAL_QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
                                                            This parameter can be a value of @ref QSPI_SampleShifting */
    uint32_t                        FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
                                                            required to address the flash memory. The flash capacity can be up to 4GB
                                                            (addressed using 32 bits) in indirect mode, but the addressable space in
                                                            memory-mapped mode is limited to 256MB
                                                            This parameter can be a number between 0 and 31 */
    HAL_QSPI_CS_HighTimeTypeDef     ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
                                                            of clock cycles which the chip select must remain high between commands.
                                                            This parameter can be a value of @ref QSPI_ChipSelectHighTime */
    HAL_QSPI_ClockModeTypeDef       ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
                                                            This parameter can be a value of @ref QSPI_ClockMode */
    HAL_QSPI_FlashBKTypeDef         FlashBKID;          /* Specifies the Flash which will be used,
                                                            This parameter can be a value of @ref HAL_QSPI_FlashBKTypeDef */
    HAL_QSPI_DualFlashTypeDef       DualFlash;          /* Specifies the Dual Flash Mode State
                                                            This parameter can be a value of @ref HAL_QSPI_DUALFLASH_Mode */
} QSPI_InitTypeDef;


/**
 * @brief  QSPI Handle Structure definition
 */
typedef struct
{
    QUADSPI_TypeDef            *Instance;        /*!< QSPI registers base address        */

    QSPI_InitTypeDef           Init;             /*!< QSPI communication parameters      */

    uint8_t                    *pTxBuffPtr;      /*!< Pointer to QSPI Tx transfer Buffer */

    __IO uint32_t              TxXferSize;       /*!< QSPI Tx Transfer size              */
    __IO uint32_t              TxXferCount;      /*!< QSPI Tx Transfer Counter           */

    uint8_t                    *pRxBuffPtr;      /*!< Pointer to QSPI Rx transfer Buffer */

    uint32_t                   Cache;            /*!< Internal cache */

    __IO uint32_t              RxXferSize;       /*!< QSPI Rx Transfer size              */
    __IO uint32_t              RxXferCount;      /*!< QSPI Rx Transfer Counter           */

#if defined(HAL_DMA_MODULE_ENABLED)
    HAL_DMA_Handle_TypeDef     *pHDMA;            /* QSPI Rx/Tx DMA Handle parameters   */
#endif  /* HAL_DMA_MODULE_ENABLED */

    __IO HAL_LockTypeDef       Lock;             /* Locking object                     */

    __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */

    __IO uint32_t              ErrorCode;        /* QSPI Error code                    */

    uint32_t                   Timeout;          /* Timeout for the QSPI memory access */
} QSPI_HandleTypeDef;

/**
 * @brief  QSPI Command structure definition
 */
typedef struct
{
    uint32_t                            Instruction;        /* Specifies the Instruction to be sent
                                                                This parameter can be a value (8-bit) between 0x00 and 0xFF */
    uint32_t                            Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
                                                                This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
    uint32_t                            AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
                                                                This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
    HAL_QSPI_AddressSizeTypeDef         AddressSize;        /* Specifies the Address Size
                                                                This parameter can be a value of @ref QSPI_AddressSize */
    HAL_QSPI_AlternateByteSizeTypeDef   AlternateBytesSize; /* Specifies the Alternate Bytes Size
                                                                This parameter can be a value of @ref QSPI_AlternateBytesSize */
    uint32_t                            DummyCycles;        /* Specifies the Number of Dummy Cycles.
                                                                This parameter can be a number between 0 and 31 */
    HAL_QSPI_InstructionModeTypeDef     InstructionMode;    /* Specifies the Instruction Mode
                                                                This parameter can be a value of @ref QSPI_InstructionMode */
    HAL_QSPI_AddressModeTypeDef         AddressMode;        /* Specifies the Address Mode
                                                                This parameter can be a value of @ref QSPI_AddressMode */
    HAL_QSPI_AlternateByteModeTypeDef   AlternateByteMode;  /* Specifies the Alternate Bytes Mode
                                                                This parameter can be a value of @ref QSPI_AlternateBytesMode */
    HAL_QSPI_DataModeTypeDef            DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
                                                                This parameter can be a value of @ref QSPI_DataMode */
    uint32_t                            NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
                                                                This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
                                                                until end of memory)*/
    HAL_QSPI_SIOOModeTypeDef            SIOOMode;           /* Specifies the send instruction only once mode
                                                                This parameter can be a value of @ref QSPI_SIOOMode */
} QSPI_CommandTypeDef;

/**
 * @brief  QSPI Auto Polling mode configuration structure definition
 */
typedef struct
{
    uint32_t                        Match;          /* Specifies the value to be compared with the masked status register to get a match.
                                                        This parameter can be any value between 0 and 0xFFFFFFFF */
    uint32_t                        Mask;           /* Specifies the mask to be applied to the status bytes received.
                                                        This parameter can be any value between 0 and 0xFFFFFFFF */
    uint32_t                        Interval;       /* Specifies the number of clock cycles between two read during automatic polling phases.
                                                        This parameter can be any value between 0 and 0xFFFF */
    uint32_t                        StatusBytesSize; /* Specifies the size of the status bytes received.
                                                        This parameter can be any value between 1 and 4 */
    HAL_QSPI_MatchModeTypeDef       MatchMode;      /* Specifies the method used for determining a match.
                                                        This parameter can be a value of @ref QSPI_MatchMode */
    HAL_QSPI_AutoPollingStopTypeDef AutomaticStop;  /* Specifies if automatic polling is stopped after a match.
                                                        This parameter can be a value of @ref QSPI_AutomaticStop */
} QSPI_AutoPollingTypeDef;

/**
 * @brief  QSPI Memory Mapped mode configuration structure definition
 */
typedef struct
{
    uint32_t                            TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
                                                                This parameter can be any value between 0 and 0xFFFF */
    HAL_QSPI_TimeoutActivationTypeDef   TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.
                                                                This parameter can be a value of @ref QSPI_TimeOutActivation */
} QSPI_MemoryMappedTypeDef;

/**
 * @}
 */

/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
 * @{
 */

/** @defgroup QSPI_ErrorCode QSPI Error Code
 * @{
 */
#define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */
#define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */
#define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */
#define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */
#define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */
#define HAL_QSPI_ERROR_NULL_POINTER     0x00000010U /*!< NULL pointer error */

/**
 * @}
 */

/** @defgroup QSPI_Flags QSPI Flags
 * @{
 */
#define QSPI_FLAG_BUSY                  QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
#define QSPI_FLAG_TO                    QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
#define QSPI_FLAG_SM                    QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
#define QSPI_FLAG_FT                    QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
#define QSPI_FLAG_TC                    QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
#define QSPI_FLAG_TE                    QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
/**
 * @}
 */

/** @defgroup QSPI_Interrupts QSPI Interrupts
 * @{
 */
#define QSPI_IT_TO                      QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
#define QSPI_IT_SM                      QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
#define QSPI_IT_FT                      QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
#define QSPI_IT_TC                      QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
#define QSPI_IT_TE                      QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
/**
 * @}
 */

/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
 * @brief QSPI Timeout definition
 * @{
 */
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE  1000U /* 1 sec */

/**
 * @}
 */

/**
 * @}
 */

/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
 * @{
 */
/** @brief Reset QSPI handle state.
 * @param  __HANDLE__ : QSPI handle.
 * @retval None
 */
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)

/** @brief  Enable the QSPI peripheral.
 * @param  __HANDLE__ : specifies the QSPI Handle.
 * @retval None
 */
#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

/** @brief  Disable the QSPI peripheral.
 * @param  __HANDLE__ : specifies the QSPI Handle.
 * @retval None
 */
#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

/** @brief  Enable the specified QSPI interrupt.
 * @param  __HANDLE__ : specifies the QSPI Handle.
 * @param  __INTERRUPT__ : specifies the QSPI interrupt source to enable.
 *          This parameter can be one of the following values:
 *            @arg QSPI_IT_TO: QSPI Timeout interrupt
 *            @arg QSPI_IT_SM: QSPI Status match interrupt
 *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
 *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
 *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
 * @retval None
 */
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))


/** @brief  Disable the specified QSPI interrupt.
 * @param  __HANDLE__ : specifies the QSPI Handle.
 * @param  __INTERRUPT__ : specifies the QSPI interrupt source to disable.
 *          This parameter can be one of the following values:
 *            @arg QSPI_IT_TO: QSPI Timeout interrupt
 *            @arg QSPI_IT_SM: QSPI Status match interrupt
 *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
 *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
 *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
 * @retval None
 */
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

/** @brief  Check whether the specified QSPI interrupt source is enabled or not.
 * @param  __HANDLE__ : specifies the QSPI Handle.
 * @param  __INTERRUPT__ : specifies the QSPI interrupt source to check.
 *          This parameter can be one of the following values:
 *            @arg QSPI_IT_TO: QSPI Timeout interrupt
 *            @arg QSPI_IT_SM: QSPI Status match interrupt
 *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
 *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
 *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
 */
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

/**
 * @brief  Check whether the selected QSPI flag is set or not.
 * @param  __HANDLE__ : specifies the QSPI Handle.
 * @param  __FLAG__ : specifies the QSPI flag to check.
 *          This parameter can be one of the following values:
 *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
 *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
 *            @arg QSPI_FLAG_SM:   QSPI Status match flag
 *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
 *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
 *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
 * @retval None
 */
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)

/** @brief  Clears the specified QSPI's flag status.
 * @param  __HANDLE__ : specifies the QSPI Handle.
 * @param  __FLAG__ : specifies the QSPI clear register flag that needs to be set
 *          This parameter can be one of the following values:
 *            @arg QSPI_FLAG_TO: QSPI Timeout flag
 *            @arg QSPI_FLAG_SM: QSPI Status match flag
 *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
 *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
 * @retval None
 */
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

/**
 *  \brief  Check QSPI in dual-flash mode or not
 *
 *  \param [in] __HANDLE__          Pointer to the QSPI Handle.
 *  \return
 *      true : in Dual-Flash mode
 *      false: in Single Flash mode
 */
#define __HAL_QSPI_IS_DUAL_FLASH(__HANDLE__)                READ_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_DFM_Msk)

/**
 *  \brief  Check which bank is targeted
 *
 *  \param [in] __HANDLE__          Pointer to the QSPI Handle.
 *  \return
 *      false: QSPI targets Bank 1
 *      true : QSPI targets Bank 2
 */
#define __HAL_QSPI_IS_FLASH_BK_2(__HANDLE__)                READ_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_FSEL_Msk)

/**
 *  \brief  Set QSPI Flash size
 *
 *  \param [in] __HANDLE__          Pointer to the QSPI Handle.
 *  \param [in] __SIZE__            flash size
 *  \return     None
 */
#define __HAL_QSPI_SET_FLASH_SIZE(__HANDLE__, __SIZE__)     WRITE_REG_MASK((__HANDLE__)->Instance->DCR, QUADSPI_DCR_FSIZE_Msk, ((__SIZE__) << QUADSPI_DCR_FSIZE_Pos))

/**
 * @}
 */

/** @addtogroup QSPI_Exported_Functions
 * @{
 */

/** @addtogroup QSPI_Exported_Functions_Group1
 * @{
 */

HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *pHQspi);
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *pHQspi);

void HAL_QSPI_MspInit(QSPI_HandleTypeDef *pHQspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *pHQspi);

/**
 * @}
 */

/** @addtogroup QSPI_Exported_Functions_Group2
 * @{
 */

/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *pHQspi);

/* QSPI indirect mode */
HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *pHQspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *pHQspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *pHQspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *pHQspi, QSPI_CommandTypeDef *cmd);
HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *pHQspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *pHQspi, uint8_t *pData);

#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *pHQspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *pHQspi, uint8_t *pData);
#endif  /* HAL_DMA_MODULE_ENABLED */

/* QSPI status flag polling mode */
HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *pHQspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *pHQspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);

/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *pHQspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);

/* Callback functions in non-blocking modes */
void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *pHQspi);
void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *pHQspi);
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *pHQspi);

/* QSPI indirect mode */
void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *pHQspi);
void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *pHQspi);
void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *pHQspi);

/* QSPI status flag polling mode */
void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *pHQspi);

/* QSPI memory-mapped mode */
void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *pHQspi);


/**
 * @}
 */

/** @addtogroup QSPI_Exported_Functions_Group3
 * @{
 */

HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *pHQspi);

uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *pHQspi);
void HAL_QSPI_ClearError(QSPI_HandleTypeDef *pHQspi);

HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *pHQspi);
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *pHQspi);

void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *pHQspi, uint32_t Timeout);

HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *pHQspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *pHQspi);

#if defined(QUADSPI_CR_DFM)
HAL_StatusTypeDef HAL_QSPI_SetFlashBankID(QSPI_HandleTypeDef *pHQspi, HAL_QSPI_FlashBKTypeDef BankID);
#endif  /* QUADSPI_CR_DFM */


/**
 * @}
 */

/**
 * @}
 */

/** @defgroup QSPI_Private_Macros QSPI Private Macros
 * @{
 */
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER)  ((PRESCALER) <= 0xFFU)

#define IS_QSPI_FIFO_THRESHOLD(THR)         (((THR) > 0U) && ((THR) <= 16U))

#define IS_QSPI_SSHIFT(SSHIFT)              (((SSHIFT) == HAL_QSPI_SAMPLE_SHIFTING_NONE) || \
                                             ((SSHIFT) == HAL_QSPI_SAMPLE_SHIFTING_HALFCYCLE))

#define IS_QSPI_FLASH_SIZE(FSIZE)           (((FSIZE) <= 31U))

#define IS_QSPI_CS_HIGH_TIME(CSHTIME)       (((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_1_CYCLE) || \
                                            ((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_2_CYCLE) || \
                                            ((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_3_CYCLE) || \
                                            ((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_4_CYCLE) || \
                                            ((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_5_CYCLE) || \
                                            ((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_6_CYCLE) || \
                                            ((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_7_CYCLE) || \
                                            ((CSHTIME) == HAL_QSPI_CS_HIGH_TIME_8_CYCLE))

#define IS_QSPI_CLOCK_MODE(CLKMODE)         (((CLKMODE) == HAL_QSPI_CLOCK_MODE_0) || \
                                             ((CLKMODE) == HAL_QSPI_CLOCK_MODE_3))

#if defined(QUADSPI_CR_DFM)
#define IS_QSPI_FLASH_ID(FLASH_ID)          (((FLASH_ID) == HAL_QSPI_FLASH_BK_1) || \
                                             ((FLASH_ID) == HAL_QSPI_FLASH_BK_2))

#define IS_QSPI_DUAL_FLASH_MODE(MODE)       (((MODE) == HAL_QSPI_DUALFLASH_ENABLE) || \
                                             ((MODE) == HAL_QSPI_DUALFLASH_DISABLE))

#endif  /* QUADSPI_CR_DFM */

#define IS_QSPI_INSTRUCTION(INSTRUCTION)    ((INSTRUCTION) <= 0xFFU)

#define IS_HAL_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == HAL_QSPI_ADDRESS_8_BITS)  || \
                                             ((ADDR_SIZE) == HAL_QSPI_ADDRESS_16_BITS) || \
                                             ((ADDR_SIZE) == HAL_QSPI_ADDRESS_24_BITS) || \
                                             ((ADDR_SIZE) == HAL_QSPI_ADDRESS_32_BITS))

#define IS_HAL_QSPI_ALTERNATE_BYTES_SIZE(SIZE)  (((SIZE) == HAL_QSPI_ALTERNATE_BYTES_8_BITS)  || \
                                             ((SIZE) == HAL_QSPI_ALTERNATE_BYTES_16_BITS) || \
                                             ((SIZE) == HAL_QSPI_ALTERNATE_BYTES_24_BITS) || \
                                             ((SIZE) == HAL_QSPI_ALTERNATE_BYTES_32_BITS))

#define IS_QSPI_DUMMY_CYCLES(DCY)           ((DCY) <= 31U)

#define IS_HAL_QSPI_INSTRUCTION_MODE(MODE)  (((MODE) == HAL_QSPI_INSTRUCTION_NONE)    || \
                                             ((MODE) == HAL_QSPI_INSTRUCTION_1_LINE)  || \
                                             ((MODE) == HAL_QSPI_INSTRUCTION_2_LINES) || \
                                             ((MODE) == HAL_QSPI_INSTRUCTION_4_LINES))

#define IS_HAL_QSPI_ADDRESS_MODE(MODE)      (((MODE) == HAL_QSPI_ADDRESS_NONE)    || \
                                             ((MODE) == HAL_QSPI_ADDRESS_1_LINE)  || \
                                             ((MODE) == HAL_QSPI_ADDRESS_2_LINES) || \
                                             ((MODE) == HAL_QSPI_ADDRESS_4_LINES))

#define IS_HAL_QSPI_ALTERNATE_BYTES_MODE(MODE)  (((MODE) == HAL_QSPI_ALTERNATE_BYTES_NONE)    || \
                                                 ((MODE) == HAL_QSPI_ALTERNATE_BYTES_1_LINE)  || \
                                                 ((MODE) == HAL_QSPI_ALTERNATE_BYTES_2_LINES) || \
                                                 ((MODE) == HAL_QSPI_ALTERNATE_BYTES_4_LINES))

#define IS_HAL_QSPI_DATA_MODE(MODE)         (((MODE) == HAL_QSPI_DATA_NONE)    || \
                                             ((MODE) == HAL_QSPI_DATA_1_LINE)  || \
                                             ((MODE) == HAL_QSPI_DATA_2_LINES) || \
                                             ((MODE) == HAL_QSPI_DATA_4_LINES))

#define IS_QSPI_DDR_MODE(DDR_MODE)          (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))

#if defined(QUADSPI_CCR_DHHC)
#define IS_QSPI_DDR_HHC(DDR_HHC)            (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))

#else
#define IS_QSPI_DDR_HHC(DDR_HHC)            (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))

#endif  /* QUADSPI_CCR_DHHC */

#define IS_QSPI_SIOO_MODE(SIOO_MODE)        (((SIOO_MODE) == HAL_QSPI_SIOO_INST_EVERY_CMD) || \
                                             ((SIOO_MODE) == HAL_QSPI_SIOO_INST_ONLY_FIRST_CMD))

#define IS_QSPI_INTERVAL(INTERVAL)          ((INTERVAL) <= QUADSPI_PIR_INTERVAL)

#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)     (((SIZE) >= 1U) && ((SIZE) <= 4U))

#define IS_QSPI_MATCH_MODE(MODE)            (((MODE) == HAL_QSPI_MATCH_MODE_AND) || \
                                             ((MODE) == HAL_QSPI_MATCH_MODE_OR))

#define IS_QSPI_AUTOMATIC_STOP(APMS)        (((APMS) ==HAL_QSPI_AUTOMATIC_STOP_DISABLE) || \
                                             ((APMS) ==HAL_QSPI_AUTOMATIC_STOP_ENABLE))

#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)    (((TCEN) == HAL_QSPI_TIMEOUT_COUNTER_DISABLE) || \
                                             ((TCEN) == HAL_QSPI_TIMEOUT_COUNTER_ENABLE))

#define IS_QSPI_FUNCTIONAL_MODE(MODE)       (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
                                             ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
                                             ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
                                             ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))


#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)      ((PERIOD) <= 0xFFFFU)

#define IS_QSPI_ALL_INSTANCE(__HANDLE__)    ((__HANDLE__) == QUADSPI0)
/**
 * @}
 */



#ifdef __cplusplus
}
#endif

#endif /* __ZB32L03x_HAL_QSPI_H */
